澳门亚洲娱乐

Verification

0checkmark澳门亚洲娱乐Independent verification can be the most effective way to ensure that your designs will meet all requirements and specifications. At Integre Technologies, we provide experienced, Senior Level dedicated resources to verify your design with a high degree of confidence. This helps ensure that your design will work correctly the first time. Integre’s Verification Services include:

Module Level Verification

  • Module Level testbench development
  • BFM/Scoreboard/Monitor development
  • Test development (directed and random)
  • Coverage analysis and debug

Chip Level Verification

  • Top Level testbench and verification environment development
  • BFM/Scoreboard/Monitor development
  • Test development (directed and random)
  • Coverage analysis and debug

System Level Verification

  • System Level testbench and verification environment development
  • BFM/Scoreboard/Monitor development
  • Integration of system level components: models and/or actual designs (i.e., multiple ASIC/FPGA designs)
  • Test development (directed and random)
  • Coverage analysis and debug

Bench Conversion

澳门亚洲娱乐Convert your existing Verilog or VHDL environment to SystemVerilog. SystemVerilog provides multiple benefits including the use of industry standard verification methodologies (OVM/UVM), and allowing you to incorporate random stimulus into your verification solution. Migrating to SV often gets pushed to a “when time permits” task, and time never permits when you have product to deliver. The Integre Bench Conversion team will migrate your environment in parallel with your product development effort, allowing your next design start to leverage the benefits of SystemVerilog.

General Verification Support Services

  • Constraint and metric based verification plan development
  • Automated regression testing and analysis
  • Bug tracking
  • Code coverage analysis
  • Functional coverage analysis
  • Formal verification (logic equivalency checking)

Tools and Languages

Integre Technologies, as an independent design services company, has expertise in a wide range of tools and languages. We will work with the tools and languages that are best for your particular application and development environment.

Languages:

Verisity (Cadence) Specman

Synopsys Vera

SystemVerilog

SystemC

Assembly Languages For CPU & BFMs

Perl, TCL/TK Scripting

Tools:

Cadence

Mentor

Synopsys

Aldec

Bugzilla And Other Error Reporting/Tracking Systems

PLI And FLI Interfaces For Custom Verification Environments

What They Say

test The expert-level verification experience of the Integre team with system-on-chip architectures enabled us to ramp up our object-oriented SOC verification effort within a few weeks of multi-site teamwork. The Integre team’s thorough work, commitment to deliver and ‘can-do’ attitude ensured a high quality design.test2
– ASIC Verification Manager